1. Field of the Invention
The present invention relates to an information processing method and an information processor for detecting redundant circuits from circuit design information, and to a program for causing a computer to execute this method.
2. Description of the Related Art
Application-Specific Integrated Circuits (ASIC) are one type of LSI (Large-Scale Integrated Circuits). To reduce the time required in circuit design for these ASIC, methods have been adopted in which the designer uses hardware description language (HDL) to describe the circuit operations, following which a computer consults a library that has been prepared in advance and produces a net list, which comprises circuit patterns that correspond to the descriptions of the circuit operations. The net list is assembled from cells that indicate configurations on the transistor level, and is substantially equivalent to data that can be copied to an exposure mask for fabricating semiconductors. From the designer's description of circuit operations, a circuit pattern of a fabrication mask is produced by computer, thus affording a major reduction in the time spent in circuit design compared with the prior art.
RTL (Register Transfer Level) is typically used as the circuit operation information for describing circuit operations by means of HDL. A simple explanation of an example of RTL follows below.
FIG. 1 shows an example of RTL description. This example shows a case in which RTL is described by Verilog-HDL. The information of input/output signals is either one of “1” and “0.”
FIG. 1 is a 1/n check circuit for checking that the output “1” is the single output for n types of input. In this case, the value of n is 4. In FIG. 1, A and B are assumed to be “0.” Since “˜X” indicates the negation of X, the “˜A” and “˜B” on the right side of the first continued assignment statement “assign” are both “˜(negation)” and therefore “1.” The S0 on the left side is therefore “1,” which is the result of the AND of “1” and “1.” The left side of the second and following continued assignment statements are “0,” and S1=S2=S3=0. Arranging S0-S3 produces “1000.” This value corresponds to the first “4′ b1000” of the “case” statement, and in this case, “DOUT=1′ b0”, resulting in the output “0.”
In this way, when A and B are applied as input under normal conditions, only one of S0, S1, S2, and S3 gives “1,” and the default in the “case” statement is not applied.
On the other hand, when an input signal is not normal due to a single stuck-at fault that occurs in the signal lines of an LSI that has been fabricated, the default within the “case” statement is applied, “1” is produced in DOUT, the check structure of the statement “assign CHECK=DOUT & ECHK” operates, and a signal that indicates the occurrence of a fault is supplied as output in “CHECK.” In the following explanation, a single stuck-at fault in which the input signal is fixed at logic value “0” is referred to as a “stuck-at-0 fault,” and a single stuck-at fault in which the input signal is fixed at logic value “1” is referred to as a “stuck-at-1 fault.”
Thus, a method is adopted for preassembling a redundant circuit that can be represented by the 1/n check circuit that is shown in FIG. 1 and thus increasing reliability. However, because this type of redundant circuit is normally a circuit that cannot exist logically, the possibility exists that logical optimization in the process of converting from RTL to a net list will eliminate redundant circuits. This possibility is illustrated by the example of the 1/n check circuit that is shown in FIG. 1.
From FIG. 1, DOUT=0 under normal conditions, and signal CHECK therefore takes the & (AND) of the numerical value “0” and ECHK. Of the two numerical values for which AND is taken, when one is “0” the value of signal CHECK is “0” regardless of the value of ECHK, and the significance of providing the statement “assign CHECK=DOUT & ECHK” is therefore canceled. This portion is therefore seen as an unnecessary circuit and is eliminated in the optimization.
As described hereinabove, some redundant circuits are provided for the sake of reliability, but others are actually logically redundant and therefore unnecessary. In either case, a redundant fault site that is recognized by a computer as a fault source such as a single stuck-at fault is contained in the RTL description. The reason for the deletion of the redundant fault site in the optimization is as follows.
As a basic optimization method of logic synthesis, for nets that indicate the physical states of connections between gates and modules, optimization is carried out such that a net in which a stuck-at-1 fault cannot be detected is replaced by a 1-clamp and a net in which a stuck-at-0 fault cannot be detected is replaced by a 0-clamp. This method is based on the fact that changing nets in which stuck-at faults cannot be detected to clamps will produce no changes in the operation of the circuit as seen from the outside. These points are described in, for example, Synthesis and Optimization of Digital Circuits by Giovanni De Micheli (USA) (McGraw-Hill, 1994. pp. 408-409; hereinbelow referred to as “Document 1”).
At the time of optimization, a computer is unable to determine whether a redundant circuit is for the purpose of reliability or simply unnecessary. To prevent the elimination of redundant circuits that are provided for the purpose of reliability, a method is described in, for example Japanese Patent Laid-Open Publication No. 102386/99 in which the designer looks at the RTL in advance and designates the circuits that are to be omitted as objects of the optimization process before the optimization process (hereinbelow referred to as “Document 2”).
In the method that is disclosed in Document 2, when there is a multiplicity of redundant circuits that are provided for the purpose of reliability, the designer is faced with the labor-intensive task of carrying out a process of finding all of these redundant circuits from among the RTL before having the computer carry out a logic synthesis if these circuits are to be protected from optimization.